Mixed Signal Design Verification Engineer
Senior

Descrizione della Posizione Lavorativa

You will join the Analog Mixed Signal Design Verification team in Livorno and be responsible for the analog/mixed-signal verification of Power Management Units for portable devices. The role focuses on ensuring top-quality, efficient verification and timely delivery by working across architectures and domains.

Responsibilities

• Define and execute comprehensive verification test plans that cover analog, digital and mixed-signal aspects.
• Work on system requirements and partner with architecture, analog, digital and software teams to ensure the design meets specifications and functions correctly.
• Design and implement testbenches and models at multiple abstraction levels to exercise target functionality.
• Create high-coverage stimulus vectors, develop tools, and implement monitors and checkers to detect issues early in the design cycle.
• Communicate verification status and results to multiple subject areas in an international context and collaborate closely with CAD and verification methodology groups.

Minimum Qualifications

• Master’s degree in Electrical Engineering or equivalent field.
• Experience in behavioral modelling using SystemVerilog and Verilog-AMS for analog, digital or mixed-signal verification environments.
• Analog and digital design background adequate to analyze verification outcomes.
• Proficiency with scripting languages (Python, Perl, TCL).
• Excellent written and verbal communication skills and a collaborative attitude for working with international teams.
• Open to experienced engineers with several years in industry or recent graduates with outstanding academic records and relevant internships.

Preferred Qualifications

• Familiarity with UVM, assertion-based verification, functional coverage and formal verification techniques.
• Understanding of AI and ML and how they can be applied to verification tasks.
• Hands-on experience in mixed-signal verification using modern EDA tools.

Benefits

• Base pay range: €72,300 – €149,300 (full-time equivalent; final pay depends on hours, skills, experience and location).
• Eligibility for discretionary Apple stock programs.
• Potential discretionary bonuses and relocation assistance where applicable.
• Comprehensive medical and dental coverage and retirement benefits.
• Employee discounts on products and reimbursement for certain formal education expenses related to career development.

Requisiti

Master’s in Electrical Engineering or equivalent; experience in behavioral modelling with SystemVerilog and Verilog-AMS; analog and digital design background; scripting skills (Python/Perl/TCL); strong written and verbal communication; experienced engineers or outstanding graduates with relevant internships considered.