Analog Layout Engineer
Senior

Descrizione della Posizione Lavorativa

Apple is building the next generation of systems‑on‑chip (SoCs) that power iconic devices. Join the Apple Silicon Engineering Group (SEG) and contribute to Analog/Mixed‑Signal (AMS) circuit evolution for elements such as SerDes, PLLs and sensors. This role focuses on converting circuit designs into manufacturable silicon layouts while working with multidisciplinary teams and advanced tools.

Role overview

As a Senior Layout Engineer you will be responsible for implementing custom analog layouts, partnering closely with circuit designers, and using sophisticated physical design and verification tools. The role offers continuous learning and collaboration across teams to optimize product performance.

Responsibilities

• Deliver Analog/Mixed‑Signal IP within an SoC flow and collaborate with cross‑functional teams to develop world‑class SoCs.
• Create advanced layouts for mixed‑signal and analog circuits, review and refine floorplans, and perform detailed circuit analysis together with designers.
• Execute full sets of design verification flows (LVS, DRC, ERC), interpret reports, and apply fixes to meet specifications and schedules.
• Plan and schedule layout activities, coordinate layout tradeoffs, and determine the fastest, most robust approaches to meet engineering goals.
• Apply analog and DFM best practices, recognize failure‑prone structures, and propose corrective layout strategies to achieve matching, low noise, and low power.

Minimum Qualifications

• Extensive experience in analog/mixed‑signal layout design, including deep submicron CMOS and significant experience with FinFET technologies.
• Proficiency in scripting/programming such as SKILL, Perl, TCL, Shell and/or Python.
• Familiarity with Machine Learning and AI concepts.
• Proven track record delivering analog layouts that achieve tight matching, low noise, and low power.
• Ability to identify failure‑prone circuit and layout structures and apply analog and DFM best practices.
• High proficiency in custom and standard‑cell floorplanning and hierarchical layout assembly.
• Technical understanding of IR drop, RC delay, electromigration, self‑heating, and coupling capacitance.
• Strong skills in interpreting physical verification reports (DRC, ERC, LVS).
• Experience using Cadence Virtuoso advanced features (XL, EAD, APR, Constraint Manager).
• Excellent communication skills and ability to collaborate with multi‑functional teams.
• Additional beneficial skills: Cadence Innovus, CAD automation experience, and PCell creation experience.

Preferred Qualifications

• B.S. in Electrical Engineering, Computer Science, or equivalent; M.S. or Ph.D. in Electrical and Computer Engineering preferred.
• Excellent knowledge of Mixed‑Signal and RF integrated circuits is helpful.
• Commitment to inclusion and diversity; Apple is an Equal Opportunity Employer and supports reasonable accommodations for applicants.

Pay & Benefits

The base pay range for this role is €69,000 to €103,500 (full‑time equivalent). Total compensation may include discretionary stock programs, bonuses, and relocation where applicable. Additional benefits include comprehensive medical and dental coverage, retirement plans, discounted products, and reimbursement for certain education expenses related to career advancement.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits and participation in discretionary stock programs
• Possible discretionary bonuses and relocation assistance
• Reimbursement for eligible educational expenses (tuition) and career development
• Employee discounts on Apple products

Requisiti

Extensive analog/mixed‑signal layout experience (deep submicron CMOS and FinFET), scripting proficiency (SKILL/Perl/TCL/Shell/Python), familiarity with ML/AI concepts, strong physical verification skills (DRC/LVS/ERC), experience with Cadence Virtuoso and related tools; B.S. in EE/CS (MSEE/Ph.D. preferred).