Mixed Signal Design Verification Engineer
Junior / Apprendista

Apple's logo

Apple

Livorno, Livorno, Toscana, Italia

Di persona

Contratto a tempo indeterminato

Hardware

Descrizione della Posizione Lavorativa

Role overview: You will join the Analog Mixed Signal Design Verification team and work alongside experienced verification engineers to deliver high-quality mixed-signal verification for Power Management Units used in portable devices.

Key responsibilities include:

  • Developing verification strategies and comprehensive test plans that cover analog, digital and mixed-signal aspects to catch issues early in the design cycle.
  • Designing and implementing test benches and models at multiple abstraction levels to validate target performance.
  • Creating high-coverage stimulus vectors, tools, monitors and checkers to verify functionality and specification compliance.
  • Focusing on system requirements and collaborating closely with architecture, analog, digital and software teams to ensure correct behavior against specifications.
  • Communicating verification status and results across multiple subject areas in an international environment and partnering with CAD and verification methodology groups.

Working approach: You will apply mixed-signal verification methodologies and state-of-the-art EDA tools to achieve efficient, high-quality verification and support timely time-to-market.

Benefits

Compensation and benefits: The role includes a base pay range and is eligible for Apple discretionary stock programs; it may also qualify for discretionary bonuses or relocation assistance. Additional benefits include comprehensive medical and dental coverage, retirement benefits, employee discounts and reimbursement for approved education related to career development.

Requisiti

Master's degree in Electrical Engineering or equivalent required; strong analog and digital design background; knowledge of scripting languages (Python/Perl/TCL); excellent written and verbal communication and ability to collaborate with international teams. Candidates may be experienced engineers with several years in industry or recent graduates with outstanding academic records and relevant internships.

Competenze richieste

  • Competenze professionali
  • Analog design Digital design Python Perl TCL SystemVerilog Verilog-AMS UVM Assertion Based Verification Functional Coverage Formal Verification Mixed-signal verification Behavioral modelling Experience with EDA tools Understanding of AI/ML applications to verification
  • Competenze trasversali
  • Teamwork Written and verbal communication Cross-team collaboration International teamwork Enthusiasm for collaboration